Titre :	Introduction to VLSI design flow
Type de document :	texte imprimé
Auteurs :	Senh Saurabh, Auteur
Mention d'édition :	First édition
Editeur :	Cambridge University Press
Année de publication :	2023
Importance :	678 P
Format :	24 X18 CM
ISBN/ISSN/EAN :	978-1-00-920081-3
Langues :	Anglais (eng) Langues originales : Anglais (eng)
Mots-clés :	Digital systems , Circuits , Logic optimization , Technology library
Index. décimale :	621
Note de contenu :	Contents. Part one : Overview of VLSI design flow.P3 1- Foundation.P3 2- Introduction to integrated circuits.P30 3- Pre-RTL methodologies.P50 4- RTL to GDS implementation flow.P69 5- Verification techniques.P83 6- Testing techniques.P91 7- Post-GDS processes.P104 Part two logic design 8- Modeling hardware using verilog.P117 9- Simulation-based verification.P147 10- RTL synthesis.P175 11- Formal verification.P210 12- logic optimization.P245 13- Technology library.P279 14- Static timing analysis.P301 15- Constraints.P335 16- Technology mapping.P363 17- Timing-driven optimizations.P383 18- Power analysis.P401 19- Power-driven optimizations.P422 Part three design for testability (DFT). 20- Basics of dft.P449 21- Scan design.P461 22- Automatic test pattern generation.P474 23- Built-in self-test.P487 Part four physical design. 24- Basic concepts for physical design.P507 25- Chip planning.P537 26- Placement.P568 27- Clock tree synthesis.P590 28- Routing.P610 29- Phsical verification and signoff.P635 30- Post-sillicon validation.P660 Index.P678

Introduction to VLSI design flow [texte imprimé] / Senh Saurabh, Auteur  . -  First édition . - [S.l.] : Cambridge University Press, 2023 . - 678 P ; 24 X18 CM.
ISBN : 978-1-00-920081-3
Langues : Anglais (eng) Langues originales : Anglais (eng)

Mots-clés :	Digital systems , Circuits , Logic optimization , Technology library
Index. décimale :	621
Note de contenu :	Contents. Part one : Overview of VLSI design flow.P3 1- Foundation.P3 2- Introduction to integrated circuits.P30 3- Pre-RTL methodologies.P50 4- RTL to GDS implementation flow.P69 5- Verification techniques.P83 6- Testing techniques.P91 7- Post-GDS processes.P104 Part two logic design 8- Modeling hardware using verilog.P117 9- Simulation-based verification.P147 10- RTL synthesis.P175 11- Formal verification.P210 12- logic optimization.P245 13- Technology library.P279 14- Static timing analysis.P301 15- Constraints.P335 16- Technology mapping.P363 17- Timing-driven optimizations.P383 18- Power analysis.P401 19- Power-driven optimizations.P422 Part three design for testability (DFT). 20- Basics of dft.P449 21- Scan design.P461 22- Automatic test pattern generation.P474 23- Built-in self-test.P487 Part four physical design. 24- Basic concepts for physical design.P507 25- Chip planning.P537 26- Placement.P568 27- Clock tree synthesis.P590 28- Routing.P610 29- Phsical verification and signoff.P635 30- Post-sillicon validation.P660 Index.P678